Sensor adjusting circuit

ABSTRACT

A sensor adjusting circuit for adjusting a digital sensor, whose circuit scale is small and which can maintain high accuracy in a wide adjustment range is provided. A sensor adjusting circuit for adjusting an analog input signal inputted from a sensor and outputting it as another analog output signal in accordance with a physical quantity to be sensed, comprises: a first analog-to-digital converter having an analog integrator ( 2 ) for integrating the analog input signal, a comparator ( 3 ) for comparing an output of the analog integrator with a predetermined value, and a D/A converter ( 7 ) for outputting an output of the comparator as the input signal; and a second digital-to-analog converter ( 5 ) for converting the output of the comparator and outputting it as the analog output signal.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a circuit which is assembled ineach of various sensors for sensing a physical quantity as an electricsignal and processes the output signal and, more particularly, to asensor adjusting circuit suitable for use in a capacitive accelerationsensor or a hot-wire air flow sensor.

[0002] In a sensor such as a capacitive acceleration sensor for sensinga physical quantity as an electric signal, it is necessary to adjust sothat the scale of the physical quantity to be sensed and the scale ofthe output signal have a desired relation.

[0003] A process necessary for satisfying the desired relation is calledscale adjustment (calibration) and a circuit assembled in a sensor forthe process is a sensor adjusting circuit. Plainly speaking, the sensoradjusting circuit is nothing but a converting circuit for givingpredetermined input/output characteristics.

[0004] The contents of the process carried out by the sensor adjustingcircuit are generally span adjustment and offset adjustment. In thiscase, the span adjustment corresponds to sensitivity adjustment, and theoffset adjustment corresponds to zero point adjustment.

[0005] A sensor adjusting circuit which uses a memory in which datanecessary to be outputted is stored in a predetermined address and makesthe address of the memory correspond to the level of an input signal,thereby outputting data to be read out as an output signal isconventional employed.

[0006] For example, Japanese Patent Application Laid-Open No. 3-51714discloses a PROM (programmable read only memory) of a Zener zappingsystem and a method of selecting a leading part of a resistor array inaccordance with the contents of data of the PROM, thereby adjusting asensor output. There is disclosed another method of adjusting an sensoroutput by changing a circuit constant of a switched capacitor circuit onthe basis of information written in the PROM.

[0007] On the other hand, for example, in Japanese Patent ApplicationLaid-Open No. 8-62010, a method of adjusting a sensor output by using anA/D converter (analog-to-digital converter) and a CPU (centralprocessing unit) is proposed.

[0008] As will be described hereinbelow, some of the conventionaltechniques do not consider limitation of expansion of the adjustmentrange and improvement in the accuracy. The other conventional techniquedoes not consider that suppression of increase in the circuit scale islimited and has a problem with improvement of the cost performance.

[0009] With respect to the conventional techniques such as the method ofselecting the leading part of the resistor array and the method ofchanging the circuit constant of the switched capacitor circuit, thecircuit structure is easily formed on a chip. When expansion of theadjustment range and increase in accuracy are attempted, however,exponential increase in the circuit scale is accompanied so that theexpansion of the adjustment range and the increase in accuracy arelimited.

[0010] As for the conventional technique of the method using the A/Dconverter and the CPU, the expansion of the adjustment range and theincrease in accuracy can be relatively easily realized. When general A/Dconverter and CPU are used, however, there is an overlapped functionpart (overhang). Consequently, an unused part in the circuit is large,the circuit scale is increased due to the unused part, and thesuppression of increase in the circuit scale is therefore limited.

SUMMARY OF THE INVENTION

[0011] It is a first object of the invention to provide a sensoradjusting circuit which can easily obtain a wide adjustment range andhigh accuracy with a small circuit scale.

[0012] It is a second object of the invention to provide a signalgenerating circuit for sensor output adjustment which does not have afunctional overhang part and has a sufficiently small circuit scalewhile maintaining the wide adjustment range and high accuracy.

[0013] The first object is achieved by a sensor adjusting circuitcomprising an analog-to-digital converter, an operational unit forprocessing an output of the analog-to-digital converter by a prestoredprogram, and a writable memory for holding data for adjustment, whereinthe analog-to-digital converter is constructed by an oversamplinganalog-to-digital converter comprising an analog integrator, a comparingcircuit, and a digital-to-analog converter.

[0014] By using the oversampling analog-to-digital converter, the numberof bits of a digital signal necessary for holding the adjustment rangeand the accuracy can be reduced. Thus, the circuit scale can besuppressed to be small.

[0015] The second object is achieved by a digital sensor adjustingcircuit for adjusting an output of a sensor which senses a physicalquantity by processing the output of the sensor by using prestored datafor characteristic adjustment, comprising: an analog integrator forintegrating outputs of the sensor and outputting resultant data; acomparator for converting and outputting the output of the analogintegrator into a digital signal of level 1 or level 0; a 1-bit D/Aconverter for converting the output of the comparator into an analogsignal and outputting the analog signal; and a subtracter forsubtracting the output of the 1-bit D/A converter from an input of theanalog integrator, wherein the output of the comparator is processedwith the prestored data for characteristic adjustment.

[0016] With the above construction, the output of the sensor forphysical detection can be digitized without using a first stageamplification circuit and an A/D converter, so that the functionaloverhang can be eliminated.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 is a block diagram showing an embodiment of a sensoradjusting circuit according to the invention;

[0018]FIG. 2 is a block diagram showing another embodiment of the sensoradjusting circuit according to the invention;

[0019]FIG. 3 is a block diagram showing further another embodiment ofthe sensor adjusting circuit according to the invention;

[0020]FIG. 4 is a block diagram illustrating the operation of anoperational unit in the embodiment of the invention;

[0021]FIG. 5 is a diagram showing the frequency characteristics of asignal in the embodiment of the invention;

[0022]FIG. 6 is a block diagram showing an embodiment when a digitalintegrator and an operational unit are constructed by an MPU in theinvention;

[0023]FIG. 7 is a block diagram showing an embodiment of a PROM in theinvention;

[0024]FIG. 8 is a block diagram showing another embodiment of the sensoradjusting circuit according to the invention;

[0025]FIG. 9 is a block constructional diagram showing an embodiment ofthe sensor adjusting circuit according to the invention;

[0026]FIG. 10 is a circuit diagram of a detection part according to anembodiment of the invention using a piezoresistance type pressuresensor;

[0027]FIG. 11 is a circuit diagram of a detection part according to anembodiment of the invention using a heat resistive type air flow ratesensor;

[0028]FIG. 12 is a block diagram showing the construction of anoperational unit according to the embodiment of the invention;

[0029]FIG. 13 is a diagram for explaining counting conditions in theoperational unit in the embodiment of the invention;

[0030]FIG. 14 is a diagram for explaining execution task switchingcontrol conditions in the operational unit according to the embodimentof the invention;

[0031]FIG. 15 is a timing chart showing the state of an internal signalin the operational unit according to the embodiment of the invention;

[0032]FIG. 16 is an explanatory diagram showing an address map of aprogram storing ROM in the embodiment of the invention;

[0033]FIG. 17 is an explanatory diagram showing the contents of bits inthe program storing ROM in the embodiment of the invention;

[0034]FIG. 18 is a diagram showing the construction of the operationalunit in the embodiment of the invention;

[0035]FIG. 19 is a block diagram showing the function of a decimator inthe embodiment of the invention; and

[0036]FIG. 20 is a block diagram of a sensor adjusting circuit accordingto another embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] The sensor adjusting circuit according to the invention will bedescribed in detail hereinbelow by embodiments shown in the drawings.

[0038]FIG. 1 shows a first embodiment of the invention, in whichreference numeral 1 denotes an analog integrator; 2 a comparator; 3 adigital integrator; 4 an operational unit; 5 a D/A converter(digital-to-analog converter); 6 an LPF (low pass filter); 7 a D/Aconverter; and 8 a PROM.

[0039] The level adjusting circuit according to the invention is mainlydivided into three kinds of functional parts. The functional parts areconstructed as described hereinbelow in the first embodiment.

[0040] The first functional part is constructed by the analog integrator1, the comparator 2, the digital integrator 3, and the D/A converter 7.

[0041] The difference between an input signal from a sensor S and anoutput of the D/A converter 7 is subjected to integration of the analogintegrator 1.

[0042] The output of the analog integrator 1 is supplied to thecomparator 2, where the output is compared with a predetermined voltageevery predetermined cycle and converted into a signal of level 0 or 1.

[0043] Further, an output of the comparator 2 is supplied to the digitalintegrator 3 and is subjected to integration and a resultant signal isoutputted as a time series digital signal of a predetermined number ofbits.

[0044] The output of the digital integrator 3 is also supplied to theD/A converter 7 and is converted into an analog signal which issubtracted from the input signal.

[0045] By the above operation, the first functional part has thefunction of outputting the time series digital signal having the numberof bits equal to that of the D/A converter 7 and whose average valuechanges according to the input signal from the digital integrator 3.

[0046] By setting the operation cycle (inverse number of the frequency)of the comparator 2 to a value as small as, for example, {fraction(1/10)} or smaller of the operation cycle (a large value of ten times orlarger in terms of frequency) determined from the response speedrequested to the sensor as an object, the first functional part displaysthe function as a so-called oversampling A/D converter. As a result,even when the number of bits of the D/A converter 7 is set to theminimum of 1 bit, principally, the necessary adjustment range andaccuracy can be assured.

[0047] This is because that the sensor adjusting circuit of theinvention realizes necessary adjustment by an operation of the averagevalue. Even if the number of bits of the D/A converter 7 is 1 bit, theaverage value of the output signal can be obtained. In this case, thedigital integrator 3 is unnecessary and it is sufficient to supply theoutput of the comparator 2 as it is to the operational unit 4 and theD/A converter 7.

[0048] It cannot be said that the case of setting the number of bits ofthe D/A converter 7 to 1 bit is very practical since a problem as willbe described hereinlater occurs. Nevertheless, according to theinvention, the number of bits such as 4 to 12 bits which is much smallerthan the number of bits estimated from the required accuracy can be set.

[0049] The second functional part is constructed by the operational unit4 and the PROM 8.

[0050] The signal outputted from the digital integrator 3 and digitaldata read from the PROM 8 is calculated by the operational unit 4,thereby varying the average value of the output signals obtained fromthe first functional part.

[0051] By the operation, the second functional part has the function ofsubstantially adjusting the zero point and the span of the output signalfrom the sensor.

[0052] In this case, since the number of bits of the signal outputtedfrom the first functional part is set to a small number of bits asdescribed above, the circuit scale of the operational unit 4 can beaccordingly reduced.

[0053] Since the digital operational process is executed, unlikeadjustment by an analog circuit device, there is not feared that aninfluence by a device variation and a change in temperature is exerted.Consequently, very accurate adjustment can be easily performed.

[0054] Lastly, the third functional part is constructed by the D/Aconverter 5 and the LPF 6.

[0055] The digital signal outputted from the operational unit 4 isconverted into an analog signal by the D/A converter 5 and the analogsignal outputted from the D/A converter 5 is smoothed by the LPF 6.

[0056] In this manner, the third functional part has the function ofconverting the digital signal obtained from the second functional partinto the analog signal, averaging the analog signal, and outputting anadjusted sensor signal.

[0057] In this case as well, as described above, since the number ofbits of the signal outputted from the first functional part is reduced,the circuit scale of the D/A converter 5 can be made small.

[0058] As mentioned above, the oversampling A/D converter comprising theanalog integrator 1, the comparator 2, the digital integrator 3, and theD/A converter 7 is used in the embodiment. As a result, even if thenumber of bits of the digital signal is reduced, the necessaryadjustment range and accuracy can be assured and the circuit scale isnot enlarged.

[0059] Since the adjusting process is carried out by a digital signal,there is not feared that an influence by variation of the circuit devicefor adjustment and a change in temperature is exerted, so that highaccuracy can be easily maintained.

[0060] The number of bits can be reduced to 1 bit as described above.

[0061] The number of bits has the trade-off relation with the number ofinput signals necessary for averaging in order to assure a desiredaccuracy. When the number of bits is reduced, the number of inputsignals for averaging has to be increased.

[0062] The time to obtain the average value is limited by the responsespeed of the sensor as an object. Consequently, with increase in thenumber of input signals, it is necessary to increase the operationalspeed of the sensor adjusting circuit itself. As a result, a heavy loadis placed especially on the operational unit 4. Since high performanceis required, the costs increase.

[0063] On the contrary, when the number of bits is set to as large as 16bits, although the operational speed of the sensor adjusting circuititself can be low, the digital integrator 3 and the operational unit 4have to proceed a large number of bits and the circuit scale istherefore increased.

[0064] In consideration of the above, in the embodiment of theinvention, it is decided that 4 to 8 bits is appropriate for the numberof bits of the D/A converter 7.

[0065] When the number of bits is set to 4 to 8 bits, the operatingspeed of the sensor adjusting circuit itself is within a practical rangeand the circuit scale is also within a proper range.

[0066] The embodiment of the invention will be described morespecifically.

[0067] According to the invention, the first functional part can beintegrated into a sensor circuit of the sensor to be combined.

[0068] Such an embodiment will be described hereinbelow.

[0069]FIG. 2 illustrates an embodiment when a capacitive sensor isapplied as a sensor to be combined.

[0070] The capacitive sensor denotes a sensor for sensing a physicalquantity to be sensed as a change in capacitance. A capacitiveacceleration sensor is typical.

[0071] In FIG. 2, reference numerals 9, 10, 12, 13, 17, and 18 denotesanalog switches; 11 a sensor capacitor; 14 a capacitor for feedback; 15an operational amplifier; and 16 a reference capacitor. Other elementsare the same as those in FIG. 1.

[0072] Each of the analog switches is constructed by a knownsemiconductor switch or the like. The analog switches are divided intotwo groups A and B and controlled. The analog switches 9, 13, and 18belong to group A and the analog switches 10, 12, and 17 belong to groupB. When the group A is controlled to be on, the group B is controlled tobe off. On the contrary, when the group A is turned off, the group B isturned on.

[0073] The sensor capacitor 11 is constructed so that its capacitancechanges according to the physical quantity to be detected. In this case,if the sensor is the acceleration sensor, the capacitance of the sensorcapacitor 11 changes according to the acceleration acting on the sensor.

[0074] The operational amplifier 15 operates as an integrator by havingthe capacitor 14 for feedback, thereby displays the same function asthat of the analog integrator 1 in the embodiment of FIG. 1.

[0075] The reference capacitor 16 is charged with an output of the D/Aconverter 7 and feeds back the output of the D/A converter 7.

[0076] The operation of the embodiment of FIG. 2 will now be described.In the embodiment, by repeating first and second operations for turningon and off the analog switches of groups A and B alternately, thecapacitance value of the sensor capacitor 11 is sensed.

[0077] The cycle for repeating the first and second operations can beset to the same as the operational cycle of the comparator 2 or shorter.

[0078] In the first operation, the analog switches 10, 12, and 17 ofgroup B are turned on.

[0079] Then the sensor capacitor 11 is discharged by the analog switches10 and 12 and the reference capacitance capacitor 16 is charged with theoutput of the D/A converter 7 via the analog switch 17.

[0080] In the second operation, the analog switches 9, 13, and 18 ofgroup A are turned on.

[0081] The sensor capacitor 11 and the reference capacitor 16 areconnected in series via the analog switches 9 and 18 between the powersource voltage Vcc and the ground. The contact point between the sensorcapacitor 11 and the reference capacitor 16 is connected via the analogswitch 13 to an inversion input of the operational amplifier 15.

[0082] The sensor capacitor 11 is charged with the power source voltageVcc and the reference capacitor 16 is discharged. The difference currentbetween the charged current of the sensor capacitor 11 and the dischargecurrent of the reference capacitor 16 is charged into the capacitor 14for feedback via the analog switch 13. As a result, a voltage accordingto the terminal voltage of the capacitor 14 for feedback appears on theoutput of the operational amplifier 15.

[0083] The voltage appeared on the output of the operational amplifier15 is supplied to the D/A

D=CsVcc/CrKda

[0084] converter 7 via the comparator 2 and the digital integrator 3 andserves as a value of the charge current to the reference capacitor 16 inthe first operation of the next cycle.

[0085] Consequently, the average value as an output of the digitalintegrator 3 is obtained by the following equation (1).   (equation 1)

[0086] where,

[0087] D: average value of outputs of the digital integrator 3

[0088] Cs: capacitance value of the sensor capacitor 11

[0089] Vcc: power source voltage

[0090] Cr: capacitance value of the reference capacitor 16

[0091] Kda: conversion coefficient of the D/A converter 7

[0092] As obviously understood from (equation 1), as an output of thedigital integrator 3 in FIG. 2, a digital signal indicative of thecapacitance value of the sensor capacitor 11 is derived. According tothe embodiment, it is therefore understood that the first functionalpart of the sensor adjusting circuit also serves as the sensor circuitof the capacitive sensor which should be assembled into the sensoradjusting circuit.

[0093] According to the embodiment of FIG. 2, therefore, the sensoradjusting circuit can have the function of the sensor circuit whichshould be assembled into the sensor adjusting circuit. As a result, thewide adjusting range and the high accuracy can be assured and thecircuit scale as a whole including the sensor circuit can besufficiently reduced.

[0094] According to the embodiment, a detection error can be alsoreduced.

[0095] When the sensor adjusting circuit and the first functional partare separately provided, errors of the respective circuits are added. Inthe embodiment of FIG. 2, however, the sensor circuit of the sensor isassembled into the first functional part, so that the error can bereduced by the feedback effect.

[0096]FIG. 3 shows an embodiment when a hot wire type air flow meterused for controlling an engine of a vehicle or the like is employed asthe sensor to be assembled. In FIG. 3, reference numerals 19 to 22denote hot wire resistors and 23 indicates a differential amplifier. Theother component elements are the same as those of the embodiment of FIG.1.

[0097] The four hot wire resistors 19 to 22 construct a bridge circuit.A voltage when the bridge circuit becomes unbalance by an air flow isdetected by the differential amplifier 23 and is outputted as adetection signal of the air flow rate. In this case, by using the outputof the D/A converter 7 as a current source of the bridge circuitconsisting of the hot wire resistors 19 to 22, both of the sensorcircuit of the hot wire type air flow meter and the first functionalpart of the sensor adjusting circuit are constructed.

[0098] Consequently, in the embodiment of FIG. 3 as well, the sensoradjusting circuit can have the function of the sensor circuit whichshould be assembled to the sensor adjusting circuit. As a result, thewide adjustment range and the high accuracy can be assured. The circuitscale as a whole including the sensor circuit can be sufficientlyreduced and, further, errors can be reduced.

[0099] The operation of the operational unit 4 in the embodiment will bedescribed with reference to the operational block diagram of FIG. 4.

[0100] As mentioned above, the operational unit 4 is a circuit foradjusting the zero point and the span of an output of the sensor as anobject by executing addition and multiplication using a predeterminedvalue to the average value of input signals (time series digital signalsas outputs of the digital integrator 3).

[0101] The adding operation for adjusting the zero point is executed asfollows. A digital processing signal line 24 which has beenpreliminarily written in the PROM 8 and has the same bit number as thatof the D/A converter 7 and whose average value is an adjustment value asan object is read out and is added to the input signal. By simpleperforming the addition, the addition to the average value of the inputsignals can be carried out without changing the number of bits.

[0102] If an overflow occurs, however, a process for correcting it isnecessary.

[0103] The multiplying operation for span adjustment is executed byreading out a digital processing signal line 25 and multiplying theinput signal by the line 25. The digital processing signal line 25 issimilarly preliminarily written in the PROM 8 and has the same number ofbits as that of the D/A converter 7. The average value of the digitalprocessing signal line 25 is an adjustment value as an object. Thefrequency characteristic of the digital processing signal line 25 is setso as not to be overlapped with a frequency distribution of the inputsignal as shown in FIG. 5. In this case as well, it is sufficient toexecute the simple multiplication.

[0104] Although the number of bits is doubled by the multiplication inthis case, since only the initial bits are effective, by cutting off thebits of the lower half, the same number of bits as that of the inputsignal can be maintained.

[0105] The reason why the frequency distributions are arranged so as notto be overlapped as shown in FIG. 5 is as follows.

[0106] When it is assumed that the frequencies of the input signal andthe digital processing signal line 25 are overlapped, a signal in theoverlapped frequency band is converted to a direct current signal by themultiplying operation and there is the possibility that the averagevalue goes wrong.

[0107] An embodiment in which the digital integrator 3 and theoperational unit 4 are constructed by an MPU (microprocessing unit) willbe described with reference to FIG. 6.

[0108] The MPU shown in FIG. 6 comprises a RAM 26 for temporarilystoring data, a PROM 27 (corresponding to the PROM 8) for storingadjustment data, an accumulator 28, an operational unit 29 for executingarithmetic operation, a controller 30, a program counter 31, and a ROM32 for storing programs. The operational unit 29, the program counter31, and a data bus are controlled by the controller 30 in accordancewith a program written in the RAM 32 and processes necessary for theoperations as the digital integrator 3 and the operational unit 4 areexecuted.

[0109] In the embodiment, the ROM 32 for storing programs is directlyaccessed by an output of the program counter 31 and output data of theROM 32 is directly outputted to the controller 30.

[0110] The instruction system in this case is one word per instruction.A backward branch instruction cannot be accepted and the maximumcounting value of the program counter 31 and the number of words of theROM 32 for storing programs are equal.

[0111] Consequently, in the embodiment, the program correctly operateswithout performing a reset, so that a reset upon the turn-on of thepower source, that is, a power-on reset process is made unnecessary.

[0112] If a reset is not executed upon turn-on of the power source, thecounting value of the program counter 31 becomes unstable and theprogram does not know from which address to start. Since there is nobackward branch instruction in the program in the embodiment, when theprogram is started, the counting value of the program counter 31 isalways increased. When the counting value reaches the maximum, itreturns to zero.

[0113] As a result, it is guaranteed that the program operates by alwayspassing the 0 address and, therefore, the reset process is notnecessary.

[0114] In the embodiment, as a matter of course, the program is limitedto a so-called cyclic program in which the address is cycled from 0 tothe maximum counting value of the program counter 31.

[0115] As the program is used only for realizing the operations of thedigital integrator 3 and the operational unit 4 in the embodiment, thefact that only the cyclic program can be used is not a limitation.

[0116] On the contrary, it also denotes that the program is not muchaffected by a runaway of the MPU. Even if the MPU runs away, thedestination address of the runaway is always an address of the programand the program is a cyclic program, so that the operation is returnedto the normal process eventually.

[0117] As it is known, it is typical that a general MPU is provided withmonitoring means such as a watch dog timer in order to certainly assurethe reset operation and deal with the runaway.

[0118] In the embodiment, however, the resetting process is unnecessaryand no problem occurs at the time of runaway of the MPU. Consequently,the monitoring means is made unnecessary. The circuit scale can bereduced and the reliability of the MPU can be improved more.

[0119] An embodiment of the PROM 8 will be described with reference toFIG. 7.

[0120]FIG. 7 shows the construction of a memory cell which is a unit ofthe PROM 8. In the embodiment, the unit memory cell is constructed bythree PROM memory cells 33, 34, and 35 and data read from them isoutputted via a majority logic circuit 36.

[0121] Generally, the PROM is easily influenced by temperature and thereliability deteriorates at high temperature.

[0122] Especially, in case of a sensor for use in an engine room of avehicle, space, and the like, it is used at high temperature, so thatthe reliability easily deteriorates.

[0123] In the embodiment of FIG. 7, therefore, data from a plurality ofmemory cells is used and the majority logic is obtained, therebyrealizing an error correction logic and an error detection logic. Thus,erroneous data is eliminated and high reliability is maintained.

[0124] Other embodiments of the invention will now be described.

[0125]FIG. 8 shows an embodiment of the invention. As shown in thediagram, a single MPU 41 is provided commonly for a plurality ofsensors, for example, three sensors A, B, and C and functions as thedigital integrator and the operational unit for the sensors by a timedivision process.

[0126]1A, 1B, and 1C are analog integrators each of which is the same asthe analog integrator 1 in the embodiment of FIG. 1. Similarly, each of2A, 2B, and 2C corresponds to the comparator 2, each of 5A and 5Bcorresponds to the D/A converter 5, each of 6A and 6B corresponds to theLPF 6, and each of 7A, 7B, and 7C corresponds to the D/A converter 7.

[0127] The MPU 41 is the one described in FIG. 6. As mentioned above,outputs of the sensors A, B, and C are sequentially time divisionprocessed in a predetermined order. Like the digital integrator 3 andthe operational unit 4 in the embodiment of FIG. 1, the MPU 41 operatesso as to adjust the zero point and the span of each sensor.

[0128] The embodiment of FIG. 8 has therefore an advantage that thecircuit scale can be reduced more than the case where the digitalintegrators 3 and the operational units 4 are provided for the pluralityof sensors, respectively.

[0129] Since the outputs from the plurality of sensors can be associatedwith each other and processed, there is an advantage that the an outputof a sensor is compensated by an output of another sensor and theembodiment can easily deal with cases where the ratio or difference ofoutputs of the plurality of sensors is necessary.

[0130] According to the embodiment of the invention as mentioned above,by using the oversampling analog-to-digital converter, the number ofbits of a digital signal necessary to assure the adjustment range andthe accuracy can be reduced. As a result, while maintaining thenecessary accuracy and adjustment range, the circuit scale can besufficiently reduced.

[0131] The sensor adjusting circuit according to another embodiment ofthe invention will be described in details by the modes shown indiagrams.

[0132]FIG. 9 shows a first embodiment of the sensor adjusting circuit ofthe invention. The sensor adjusting circuit of the embodiment isconstructed mainly by parts of the following three kinds of functions.

[0133] The first part is a part having both of the functions of a firststage amplifier and an A/D converter and comprises a subtracter 1′, theanalog integrator 1, the comparator 2, and the 1-bit D/A converter 7.

[0134] The subtracter 1′ has the function of subtracting an output ofthe 1-bit D/A converter 7 from a detection signal of a sensor (physicalquantity sensing device) S.

[0135] The analog integrator 1 has the function of receiving andintegrating the difference between an output signal of the sensor S andthe output of the 1-bit D/A converter 7 from the subtracter 1′.

[0136] The comparator 2 has the function of comparing an output voltageof the analog integrator 1 with a predetermined reference voltage andconverting to a 1-bit signal of level 1 or 0.

[0137] The 1-bit D/A converter 7 has the function of converting theoutput of the comparator 2 into an analog voltage and supplies theanalog voltage to a negative (−) input terminal of the subtracter 1′.

[0138] As a result, an output signal (A) whose pulse density changesaccording to the signal sensed by the sensor S is obtained from thecomparator 2.

[0139] A circuit for generating an output signal whose pulse densitychanges according to an input signal is called a ΔΣ modulator. In theinvention, the signal supplied from the sensor S is modulated by usingthe modulator, thereby enabling the number of bits of the output of thesensor to be reduced.

[0140] The second part is a part having the function of adjusting thespan and the zero point and is constructed by the operational unit 4which is operated by an internal program and the PROM 8 in whichpredetermined data has been preliminarily written.

[0141] The operational unit 4 calculates the average value of the pulsedensity modulated output signals (A) obtained by the first functionalpart and executes an arithmetic operation to the average value of theoutput signals and the data stored in the PROM 8, thereby adjusting thespan and the zero point of the output signal of the sensor S.

[0142] As mentioned above, since the output of the sensor S is processedby the digital arithmetic operation, unlike the adjustment by the analogdevice, the influence by the variation in devices and the change intemperature is not exerted. Consequently, the adjustment with extremelyhigh accuracy can be realized.

[0143] Since the signal supplied from the sensor S is modulated and thenumber of bits is reduced, the circuit scale of this part is reduced.

[0144] The operation for obtaining the average value of the modulatedsignal (decimation operation) is also executed by the internal programof the MPU 4, so that the circuit scale can be also reduced from thispoint.

[0145] The third part is a part having the D/A converting function andis constructed by a PWM (pulse width modulator) 5′ and the LPF (low passfilter) 6.

[0146] The PWM 5′ outputs a signal whose pulse width is modulatedaccording to the digital signal outputted from the operational unit 4,that is, a pulse width modulation signal. The LPF 6 averages the pulsewidth modulation signals outputted from the PWM 5′ and generates analogsignals.

[0147] Consequently, the D/A converting function is obtained by the PWM5′ and the LPF 6 and an output signal is derived with high accuracy byperforming the span and zero point adjustment to the output signal fromthe sensor S.

[0148] A specific example of the first part in the foregoing embodimentof the invention will be described with reference to FIGS. 10 and 11.

[0149]FIG. 10 shows an embodiment in which the invention is applied to apressure measuring apparatus using a piezoresistive pressure sensor SPas a physical quantity sensing device. FIG. 11 shows an embodiment inwhich the invention is applied to an air flow rate measuring apparatususing a heat resistive air flow rate sensor SF as a physical quantitysensing device.

[0150] The embodiment of FIG. 10 will be described first. The pressuresensor SP comprises a bridge circuit constructed by four resistors 115,116, 117, and 118 which are piezoresistive devices. The balance state ofthe bridge circuit changes according to a pressure acting on a pressurereceiving part of the sensor, thereby obtaining an output voltageindicative of the pressure.

[0151] The operation of the embodiment will be explained. The circuitcomprises six analog switches 119, 120, 122, 123, 129, and 130. Byrepeating two kinds of first and second operations, the switches areopened and closed. In the first operation, the analog switches 120, 122,and 129 are closed and the analog switches 119, 121, and 130 are opened.

[0152] By the operation, a capacitor (capacitive device) 121 is chargedup with a voltage appearing between the resistors 115 and 116 in thepressure sensor SP and a capacitor 128 is charged up with an outputvoltage Va of a 1-bit D/A converter 131.

[0153] In the second operation, the analog switches 120, 122, and 129are opened and the analog switches 119, 121, and 130 are closed.

[0154] By the operation, the capacitor 21 is charged up with a voltageacross the resistors 17 and 18 and the voltage of the capacitor 121 isswitched from the voltage across the resistors 115 and 116 to thevoltage across the resistors 117 and 118.

[0155] The charge amount according to the change in voltage across bothterminals of the capacitor 121 and the capacitance value of thecapacitor 121 is supplied to an operational amplifier 125 via an analogswitch 123 and an integrator constructed by the operational amplifier125 and a capacitor 124 is charged with the charge amount.

[0156] The capacitor 128 is charged with an output voltage Vb of the1-bit D/A converter 131, so that a voltage across the terminals of thecapacitor 128 is switched from the voltage Va to the voltage Vb.

[0157] A charge amount according to the change in the voltage across theterminals of the capacitor 128 and the capacitance value of thecapacitor 128 is inputted via the analog switch 123 to the operationalamplifier 125 and the integrator constructed by the operationalamplifier 125 and the capacitor 124 is charged up.

[0158] The integrator constructed by the operational amplifier 125 andthe capacitor 124 is therefore charged with charges according to thevoltage of the bridge circuit of the pressure sensor SP and thedifference between the output voltages Va and Vb of the 1-bit D/Aconverter 131. The result is reflected in the output of the integratorconstructed by the operational amplifier 125 and the capacitor 124.

[0159] The output is supplied to a comparator 126 and is binarized. Thebinarized data is held by a DFF (D flip flop) 127 so that the result canbe reflected upon the next charging operation.

[0160] An output of the DFF 127 is inputted to the 1-bit D/A converter131, so that the outputs Va and Vb are changed accordingly.

[0161] For example, when the output of the DFF 127 is 1, the output Vaof the 1-bit D/A converter 131 becomes a reference voltage V1 and theoutput Vb becomes a reference voltage V2. When the output of the DFF 127is 0, the output Va becomes the reference voltage V2 and the output Vbbecomes the reference voltage V1.

[0162] By repeating the first and second operations, the average valueof the output voltages of the integrator constructed by the operationalamplifier 125 and the capacitor 124 is converged on 0. As a result, theaverage value of the voltages of the outputs Va and Vb of the 1-bit D/Aconverter 131 coincides with the output voltage of the pressure sensorSP.

[0163] When the average value of the voltages between the outputs Va andVb is set to be proportional to the average value of outputs of the DFF127, by digitally obtaining the average value of the outputs of the DFF127, the output voltage of the pressure sensor SP can be derived.

[0164] The degree of change in the average value of the output voltagesof the DFF 127 is determined how the voltages at the outputs Va and Vbof the 1-bit D/A converter 131 are changed, namely, how each of thereference voltages V1 and V2 and the difference of the voltages aredecided.

[0165] If the change amount of the outputs Va and Vb of the 1-bit D/Aconverter 131 with respect to the output of the DFF 127 is reduced, thechange ratio of the average value of the output of the DFF 127 withrespect to the change in the bridge voltage of the pressure sensor SPcan be increased.

[0166] Since the outputs of the DFF 127 have levels of “1” and “0” only,the range of the average value L is 0>L<1.

[0167] If the sensitivity to the bridge voltage of the pressure sensorSP is increased, the measurement range is narrowed. Contrarily, when thechange amount of the outputs Va and Vb of the 1-bit D/A converter 131 isincreased, although the change ratio of the average value of the outputsof the DFF 127 with respect to the change in the bridge voltage of thepressure sensor SP is reduced, the measurement range is widened.

[0168] In other words, the optimum change voltage can be applied to theoutputs Va and Vb of the 1-bit D/A converter 131 in accordance with themaximum change amount of the bridge voltage of the pressure sensor SP,so that the measurement range which cannot be changed and expanded by ageneral A/D converter can be easily changed and expanded.

[0169] The input range of a general A/D converter usually corresponds tothe power source voltage. On the contrary, the change in the bridgevoltage of the pressure sensor SP is tens mV. When a general A/Dconverter is used, an amplification circuit is therefore necessary atthe first stage as mentioned above.

[0170] In the embodiment, however, by applying a predetermined changevoltage to the outputs Va and Vb of the 1-bit D/A converter 131, thevoltage level can be easily adjusted. Consequently, a preamplifier ismade unnecessary.

[0171] Since the input impedance of the circuit is determined by thecapacitor 121 in the embodiment, a relatively high input impedance canbe easily obtained. Consequently, from the viewpoint of the impedanceconversion as well, the amplification circuit at the first stage can bemade unnecessary.

[0172] According to the embodiment, the outputs Va and Vb of the 1-bitD/A converter 131 can also have a temperature characteristic.Temperature compensation can be therefore carried out in such a mannerthat the temperature characteristic opposite to that of the pressuresensor SP or that of the circuit is added to the output characteristicsof the 1-bit D/A converter 131 to thereby offset the temperaturecharacteristic of the pressure sensor SP or the temperaturecharacteristic of the circuit.

[0173] An embodiment of FIG. 11 will now be described.

[0174] The embodiment of FIG. 11 is different from FIG. 10 with respectto the points such that the air flow rate sensor SF is used in place ofthe pressure sensor SP in the embodiment of FIG. 10 and a 1-bit D/Aconverter 131 a is employed instead of the 1-bit D/A converter 131. Theother construction and operation are the same, so that their descriptionis omitted here. Only the different points will be describedhereinbelow.

[0175] The heat resistive air flow rate sensor SF senses the air flowrate by measuring a radiation amount generated by the air flowing on thesurface of a hot wire resistive element 135, thereby measuring the airflow rate. In practice, a current is flowed to the hot wire resistiveelement 135, the hot wire resistive element 135 is heated by Joule heatgenerated by the current and is controlled so that the temperaturebecomes constant, a radiation amount generated by the flow of air andthe heating amount by the Joule heat generated by the current arebalanced and the value of the current required for the heating ismeasured, thereby measuring the air flow rate.

[0176] For this purpose, the air flow rate sensor SF comprises: atransistor 132 for controlling the current supplied to the hot wireresistive element 135; resistive elements 133, 134, and 136 for formingthe bridge circuit together with the hot wire resistive element 135; anda differential amplification circuit 139 for detecting the bridgevoltage of the bridge circuit and controlling the transistor 132.

[0177] Like the hot wire resistive element 135, the resistive element133 is arranged in a passage of air to be measured, detects the airtemperature by using the fact that a value of resistance changesaccording to the temperature of air, and is subjected to temperaturecompensation. The sensor output is generated as a signal between theconnection point of the hot wire resistive element 135 and the resistiveelement 136 and the ground (common potential).

[0178] The 1-bit D/A converter 131 a is basically the same as the 1-bitD/A converter 131 in the embodiment of FIG. 10. In the case of FIG. 11,the output of the air flow rate sensor SF is generated as a signal whichuses one of the levels as a common potential.

[0179] The 1-bit D/A converter 131 a in the embodiment of FIG. 11generates the output Va of a predetermined voltage value when the outputof the DFF 127 is at the level 1 but does not generate a signal when theoutput of the DFF 127 is at the level 0.

[0180] Accordingly, one end of each of the analog switches 120 and 130is connected to the ground and an earth potential is received as anoutput Vb.

[0181] In the embodiment of FIG. 11 as well, by applying a proper changevoltage to the 1-bit D/A converter 131 a and generating the output Va ofa predetermined voltage to the earth voltage (0 voltage), therebyenabling the amplification circuit at the first stage to be eliminated.The other advantages as those of the embodiment of FIG. 10 can be alsoobtained.

[0182] Referring again to FIG. 9, the second part will be described.

[0183] The operational unit 4 in the second part has the construction asshown in FIG. 12 and executes four kinds of tasks time divisionally asdescribed hereinbelow.

[0184] The first task is the task for decimation and interpolation. Thedecimation is a process for calculating the average value of the outputsignals of the comparator 2. The interpolation is a process formodulating a signal outputted from a sensor such as the pressure sensorSP or the air flow rate sensor SF to reduce the number of bits. Thefirst task is executed with the highest priority.

[0185] The second task is the task for reading the contents written inthe PROM 8, executing an arithmetic operation to the information and theaverage value of the output signals of the comparator 2 obtained by thefirst task, and adjusting the span and the zero point of the signaloutputted from the sensor.

[0186] The third task is a subroutine process of the second task and thetask for executing multiplication.

[0187] The fourth task is the task for executing a process which isactivated when an external signal PROM_WRITE becomes at the low level,receives information from an SCI (serial communication interface), andwrites the information to the PROM 8.

[0188] The execution of the tasks is controlled by a dip switch 151, aPCCR (program counter control register) 152, PCs (program counters) 154,155, 156, and 157, a control unit 153, and a program storing ROM addressgenerator 158.

[0189] A control signal of the internal bus and a signal of an addressbus are generated by a program storing ROM 159. According to thecontents of the control signal and the address bus signal, data istransferred among an accumulator 160, an operational unit 161, a counter162, a serial communication control part 163, a RAM (random accessmemory) 164, a ROM (read only memory) 165, an output port 166, a switchcircuit 167, and the PCCR (program counter control register) 152 whichare connected to the internal buses (the control signal bus, addressbus, and data bus). The switch circuit 167 switches a RAM 168 and thePROM 8 (FIG. 16) which are connected to the circuit 167 and a bufferoperation.

[0190] The operation of the operational unit 4 will now be described.

[0191] The operation of the control unit 153 will be explained first. Asa first operation, the control unit 153 controls the PCs 154, 155, 156,and 157. As a second operation, the control unit 153 generates taskexecution signals to control the execution of the four kinds of tasks.

[0192] The first operation of the control unit 153, that is, theoperation for controlling the PCs 154, 155, 156, and 157 will bedescribed.

[0193] The control unit 153 generates signals for controlling stoppingand executing a counting operation to the PCs 154, 155, 156, and 157 bya logic shown in FIG. 6.

[0194] For the PC 154, as shown in FIG. 13A, a signal for counting upthe counter 154 when an external signal PROM_WRITE is at the high levelis generated.

[0195] As shown in FIG. 13B, the PC 155 is counted up when the externalsignal PROM_WRITE is at the high level, the counting value of the PC 154is larger than a preset value of the dip switch 151, the counting valueof the PC 156 is the maximum value, and the bit 0 of the PCCR 152 is “1”or the counting value of the PC 155 is not the maximum value.

[0196] As shown in FIG. 13C, the PC 156 is counted up when the externalsignal PROM_WRITE is at the high level, the counting value of the PC 154is larger than the preset value of the dip switch 151, and the bit 1 ofthe PCCR 152 is “1” or the counting value of the PC 156 is not themaximum value.

[0197] As shown in FIG. 13D, the PC 157 is counted up when the externalsignal PROM_WRITE is at the low level.

[0198] The second operation of the control unit 153, that is, thegeneration of the task execution signals will be described. The controlunit 153 generates execution signals for four tasks by the logic asshown in FIG. 14.

[0199] As shown in FIG. 14A, the execution signal for the first task isgenerated when the external signal PROM_WRITE is at the high level andthe counting value of the PC 154 is equal to or smaller than the setvalue of the dip switch 151.

[0200] As shown in FIG. 14B, the execution signal for the second task isgenerated when the external signal PROM_WRITE is at the high level, thecounting value of the PC 154 is larger than the preset value of the dipswitch 151, and the counting value of the PC 156 is at the maximumvalue.

[0201] As shown in FIG. 14C, the execution signal for the third task isgenerated when the external signal PROM_WRITE is at the high level, thecounting value of the PC 154 is larger than the set value of the dipswitch 151, and the counting value of the PC 156 is not at the maximumvalue.

[0202] As shown in FIG. 14D, the execution signal for the forth task isgenerated when the external signal PROM_WRITE is at the low level.

[0203] How the four kinds of tasks are executed by the above operationof the control unit 153 will be described by a timing chart of FIG. 15.

[0204] At timing 1, the external signal PROM_WRITE is at the high leveland the counting value of the PC 154 is equal to or lower than thepreset value of the dip switch 151, so that only the PC 154 is countedand the first task is executed. Since the preset value of the dip switch151 is set at the end address of the first task program, the first taskprogram starts at the timing 1 and is executed until the end.

[0205] At timing 2, the external signal PROM_WRITE is at the high leveland the counting value of the PC 154 becomes larger than the presetvalue of the dip switch 151, so that the execution signal for the secondtask becomes true. At this moment, however, the bit 0 of the PCCR 152 is“0” and counting of the PC 155 is stopped. The second task is thereforenot yet executed.

[0206] At timing 3, the external signal PROM_WRITE is at the high leveland the PC 154 is overflowed and its counting value is returned to 0 andis smaller than the preset value of the dip switch 151. Only the PC 154is therefore counted and the first task is executed.

[0207] At timing 4, similar to timing 2, the execution signal for thesecond task becomes true. Since “1” is written to the bit 0 of the PCCR152 by the first program at timing 3, the PC 155 is started to becounted and the second task is executed.

[0208] At timing 5, the first task is executed and the second task isstopped in the middle. The second task is again executed at timing 6.

[0209] At timing 6, as shown in the diagram, the second task is executedin the beginning. Since “1” is written to the bit 1 of the PCCR 152 bythe second task, execution of the third task is started and is continuedthrough timing 6 and until the start point of timing 7. The third taskis stopped at the start point of timing 7.

[0210] At timing 7, similar to timing 1, the first task operates.

[0211] At timing 8, the third task is executed again and is stoppedagain in the middle at the end of timing 8.

[0212] At timing 9, the first task is executed again.

[0213] At timing 10, the third task is executed again. Upon the end ofthe third task, the continuation of the second task is executed.

[0214] At timing 11, the external signal PROM_WRITE becomes at the lowlevel, so that the fourth task operates.

[0215] As shown in the diagram, therefore, the first task is executed ina constant cycle according to the counting of the PC 154 when theexternal signal PROM_WRITE is at the high level.

[0216] The second and third tasks are executed in the idle time of thefirst task. The start of the second task is controlled by the first taskand the start of the third task is controlled by the second task.

[0217] The fourth task is controlled by the external signal PROM_WRITE.

[0218] The operation of the program storing ROM address generator 158will be described. The program storing ROM address generator 158 has thefunction of generating an address sinal of a program storing ROM 159.

[0219]FIG. 16 is an address map of the program storing ROM 159. As shownin the diagram, the program of the first task is stored in addresses 000to 0FF. Similarly, the program of the second task is stored in addressesfrom 100 to 1FF, the program of the third task is stored in addressesfrom 200 to 3FF, and the program of the fourth task is stored inaddresses from 400 to 4FF.

[0220] The program storing ROM address generator 158 generates addresssignals of the program storing ROM 159 from the execution signals forthe tasks generated from the control unit 153 and the counting values ofthe PCs 154, 155, 156, and 157 as will be described hereinbelow.

[0221] When the execution signal for the first task is true, the upperthree bits of the address signal of the program storing ROM 159 are setto “000”. With respect to the lower 8 bits of the address signal of theprogram storing ROM 159, the counting value of the PC 157 is used as theaddress signal.

[0222] When the execution signal for the second task is true, the upperthree bits of the address signal of the program storing ROM 159 are setto “000” and the counting value of the PC 155 is used as the lower 8bits of the address signal of the program storing ROM 159.

[0223] When the execution signal for the third task is true, the uppertwo bits of the address signal of the program storing ROM 159 are set to“01” and the counting value of the PC 142 is used as the lower 9 bits ofthe address signal of the program storing ROM 159.

[0224] When the execution signal for the fourth task is true, the upperthree bits of the address signal of the program storing ROM 159 are setto “101” and the counting value of the PC 157 is used as the lower 8bits of the address signal of the program storing ROM 159. As mentionedabove, the address signal of the program storing ROM 159 is generatedfrom each of the counting values of the PCs 154, 155, 156, and 157 andthe execution signal for the task.

[0225] The operation of the program storing ROM 159 will be explained.

[0226] In the bit structure of the program storing ROM 159, as shown inFIG. 17, the 7th bit is for an instruction code and the 6th to 0th bitshave the bit structure expressing the execution address. One word isused for one instruction.

[0227] When the instruction code is “1”, an operation for transferringdata from a device designated by the execution address to an accumulator160 is executed. When the instruction code is “0”, an operation fortransferring data from the accumulator 160 to a device designated by theexecution address is carried out.

[0228] Consequently, the control signal of the internal bus and thesignal of the address bus can be generated as follows.

[0229] As the signal of the address bus, data from bit 6 to bit 0 in theprogram storing ROM 159 is outputted as it is.

[0230] As the control signal (read and write signals), the data of bit 7in the program storing ROM 159 is outputted as it is.

[0231] According to the embodiment, therefore, the control signal of theinternal bus and the signal of the address bus can be generated only bythe above operation.

[0232] The operational unit 161 will now be described. The operationalunit 161 has the logic structure shown in FIG. 18 and supports theprocesses of addition, AND operation, inversion, arithmetic right shift,and arithmetic left shift.

[0233] The adding operation is executed as shown in FIG. 18 in such amanner that the contents of a register 169 which is connected to theinternal bus and has a predetermined address, and to/from which data canbe inputted/read are added to the contents of the accumulator 160 by anadder 170 and the result of the addition is supplied to an output port175 which is connected to the internal bus and has a predeterminedaddress.

[0234] For the adding operation, therefore, it is sufficient to transferaddition data to the register 169, transfer the data to be added to theaccumulator 160, and read the output port 175. The addition result canbe obtained only by the operation.

[0235] The adder 170 deals the data with complement on two. When anoverflow or underflow occurs, the maximum positive number or the maximumnegative number is set. Consequently, overflow and underflow processesare made unnecessary in the program.

[0236] According to the embodiment, therefore, although versatility forthe data length is reduced, the number of steps of the program can bereduced and the execution time can be shortened for an application inwhich the data length is fixed.

[0237] The AND operation will be described.

[0238] In case of AND operation, similar to the adding operation, thecontents of the accumulator 160 and the contents of the register 169 aresupplied to an AND operational unit 171 and the result of the ANDoperation is outputted to an output port 176.

[0239] For the AND operation, it is sufficient to transfer the AND datato the register 169, transfer data to be subjected to the AND operationto the accumulator 160, and read the output port 176. The AND result canbe obtained by the operation.

[0240] In the inverting operation, the contents of the accumulator 160are supplied to an inversion operational unit 172 and the result of theinverting operation is outputted to an output port 177. For theinverting operation, therefore, it is sufficient to transfer data to beinversion operated to the accumulator 160 and read the output port 177.The result of the inverting operation can be easily obtained.

[0241] In the arithmetic right shift operation, the contents of theaccumulator 160 are inputted to an arithmetic right shift operationalunit 173 and the result of the arithmetic right shift operation isoutputted to an output port 178. For the arithmetic right shiftoperation, it is therefore sufficient to transfer data to be subjectedto the arithmetic right shift operation to the accumulator 160 and readthe output port 178. The result of the arithmetic right shift operationcan be obtained only by the operation.

[0242] In the arithmetic left shift operation, the contents of theaccumulator 160 are inputted to an arithmetic left shift operationalunit 174 and the result of the arithmetic left shift operation isoutputted to an output port 179. For the arithmetic left shiftoperation, it is therefore sufficient to transfer data to be subjectedto the arithmetic left shift operation to the accumulator 160 and readthe output port 179. The result of the arithmetic left shift operationcan be easily obtained by the operation.

[0243] The operation of a register 169 will now be described.

[0244] When the contents of the register 169 are in a predeterminedstate or the state of the task execution signal is in a predeterminedstate, the register 169 is controlled to be write inhibited on the basisof the existence or absence of occurrence of a carry in the operationalunit 161. With the structure, a branching process necessary for thearithmetic operation can be falsely realized.

[0245] The condition of the write inhibition is not limited by theexistence or absence of the carry. Similarly, writing can be inhibitedby occurrence of an overflow, writing of predetermined data to apredetermined register, and the like. Consequently, the operation of aprogram counter accompanying the branching operation is made unnecessaryand the logic scale of the program counter can be reduced.

[0246] The characteristics of the operational unit 4 in the embodimentwill be described. The first characteristic is that a resettingoperation is unnecessary.

[0247] In a case of a conventional technique using a regular MPU(microprocessing unit), the resetting operation is always required bythe following reasons.

[0248] In the conventional technique, the program storing ROM isconnected to the same bus to which a data storing ROM, a RAM, an I/O areconnected. Consequently, if the resetting operation is not performed,the initial value of the program counter becomes unstable. There is thepossibility that the initial value of the program counter indicates thedata storing ROM, RAM, or I/O.

[0249] As for the instruction word lengths, there are instructions ofone, two, and three words. The length is different according to aninstruction code and an addressing mode. Consequently, even if theinitial value of the program counter indicates the program storing ROMby chance, it does not always indicate the address including theinstruction code.

[0250] Since the backward branch instruction is generally supported,even if the initial value of the program counter indicates theinstruction code of the program storing ROM by chance, there is thepossibility to enter an endless loop.

[0251] Further, in the conventional MPU, the number of instruction codesis large and the number of addressing modes is large. Consequently, aninstruction decoder itself for analyzing an instruction needs theresetting operation.

[0252] An application program is generally made on the premise of theinitial process, so that the initial value of the program counter has tobe set to a predetermined value. Consequently, the reset isindispensable.

[0253] Due to the resetting function, however, a general MPU always hasthe danger of runaway. For an application which requires strictreliability, therefore, a watch dog timer or the like is provided as acountermeasure for the runaway. The cost of the countermeasure for therunaway is too high to ignore and increase in cost is unavoidable.

[0254] The invention realizes the operational unit which does notrequire the resetting operation. Since the resetting operation can bemade unnecessary, the danger of runaway is eliminated. Thecountermeasure for runaway such as a watch dog timer is unnecessary andthe operational unit can be applied to a cheap product.

[0255] The reason why the resetting operation is unnecessary in theoperational unit 4 according to the embodiment of the invention will bedescribed hereinbelow.

[0256] The program storing ROM is connected to a data bus which isdifferent from the bus to which the data storing ROM, RAM, I/O and thelike are connected.

[0257] As a result, the possibility that the initial value of theprogram counter indicates the data storing ROM, RAM, and I/O can beeliminated.

[0258] The length of instruction word is fixed to one word, so that theinitial value of the program counter always indicates the addressincluding the instruction code.

[0259] The backward branch instruction can be also eliminated.

[0260] Generally, since it is necessary to form a loop in an applicationprogram, the backward branch is always necessary.

[0261] Since a repeating control is executed in the operational unit 4in the embodiment of the invention as well, a loop is necessary. Byusing the fact that the counting value of the counter is returned to “0”when each of the program counters 154, 155, 156, and 157 is overflowed,a loop for the repeating control is obtained.

[0262] In the operational unit 4, two kinds of instruction codes of aload (data transfer to the accumulator) and a store (data transfer fromthe accumulator) are used, only direct addressing is employed as theaddressing mode, and only one accumulator is used.

[0263] With the structure, the instruction decoder itself is madeunnecessary and the logic can be simplified, thereby realizing a logicstructure which does not require the resetting operation.

[0264] According to the embodiment, the application program is limitedto adjustment of the zero point and the span of the sensor, calculationfor the filtering process, and the like and does not requireinitialization.

[0265] No problem occurs if the application program can be executed fromany part with respect to the adjustment of the zero point and the spanof the sensor.

[0266] The second characteristic is that two kinds of instruction codesof loading (data transfer to the accumulator) and storing (data transferfrom the accumulator) are used and the instruction decoder is notemployed. Consequently, reduction in the logic scale can be realized andthe above-mentioned resetting operation can be made unnecessary.

[0267] Specifically, the above is achieved by adopting the operationalunit 161 as shown in FIG. 12.

[0268] That is, by using the operational unit 161, even if there are twokinds of the instruction codes of loading and storing, the arithmeticoperations such as addition, AND operation, inversion, arithmetic rightshift and arithmetic left shift can be realized.

[0269] Specifically, the branch process is falsely realized by adoptingthe register 169 as shown in FIG. 18, so that the inherent branchprocess is unnecessary. Consequently, only two kinds of the instructioncodes of loading and storing of the operational unit 4 are sufficient.

[0270] The third characteristic is that four kinds of tasks are operatedtime divisionally with a simple circuit construction in the operationalunit 4 according to the embodiment of the invention. The four programcounters (PCs) 154, 155, 156, and 157 are provided and the four kinds oftasks are executed by the four PCs, thereby enabling complicatedprocesses to be executed with a simple circuit construction.

[0271] The first task can be regarded as a timer interrupting process.The third task can be regarded as a subroutine process. The fourth taskcan be regarded as an interrupting process by an external signal.Therefore, the complicated operation can be carried out with the simplecircuit construction.

[0272] The operation as a decimator of the operational unit 4 of theembodiment will be described with reference to FIG. 19.

[0273]FIG. 19 is a block diagram showing the function of the decimator.The decimator in the embodiment comprises an FIR filter 180, an IIRfilter 181, and an FIF filter 183 each having unit delay circuits Z⁻¹.

[0274] The FIR filter 180 is a part having the function of generating1-bit signals of levels 1 and 0 outputted from the comparator 2 (FIG. 3)in a predetermined cycle every 8 cycles and supplying the signals to theIIR filter 181. Specifically, the above operation is realized by thecounter 162 (FIG. 12) which is reset every 8 cycles and is counted upwhen the output of the comparator 2 is “1”.

[0275] The IIR filter 181 and the FIR filter 183 are realized by thefirst task of the application program of the operational unit 4. The IIRfilter 181 is provided with a significant digit cancellationcompensating circuit 182 for compensating cancellation of significantdigits.

[0276] The decimator is usually constructed by an FIR filter. Theconstruction is, however, realized only by an extremely large-scaledlogic circuit since the characteristic deteriorates due to thecancellation of significant digits.

[0277] According to the invention, however, by additionally providingthe significant digit cancellation compensating circuit 182, thedeterioration of the characteristic occurred by the cancellation ofsignificant digits can be reduced. Thus, as shown in the diagram, thedecimator is easily realized by a simple logic circuit.

[0278] Another embodiment of the sensor adjusting circuit of theinvention will be described with reference to FIG. 20.

[0279] Although the signal process of the single sensor S is executed bythe operational unit 4 in a one-to-one corresponding manner in theembodiment of FIG. 9, the signal process for a plurality of sensors canbe also carried out by a single operational unit 4 depending on itsprocessing ability. In the embodiment as shown in FIG. 20, a firstpressure sensor SP1, a second pressure sensor SP2, and a temperaturesensor ST are controlled by a signal operational unit 4.

[0280] An output of the first pressure sensor SP1 is modulated by a partcomprising a subtracter 1A, an analog integrator 1A, a comparator 2A,and a 1-bit D/A converter 7A and is supplied as a signal A1 to theoperational unit 4.

[0281] Similarly, an output of the second pressure sensor SP2 ismodulated by a part comprising a subtracter 1B, an analog integrator 1B,a comparator 2B, and a 1-bit D/A converter 7C and is supplied as asignal A2 to the operational unit 4.

[0282] An output of the temperature sensor ST is modulated by a partcomprising a subtracter 1C, an analog integrator 1C, a comparator 2C,and a 1-bit D/A converter 7C and is supplied as a signal T to theoperational unit 4.

[0283] The operational unit 4 sequentially receives the signals A1, A2,and T time divisionally and executes the following arithmeticoperations.

[0284] For the output of the first pressure sensor SP1, correction datafor the first pressure sensor SP1 is read from the PROM 8, the span andthe zero point are nonlinearly adjusted, a process for correcting thetemperature by the output of the temperature sensor ST is executed, theprocessed signal is outputted to the PWM 5A, and an output 1 is obtainedfrom the LPF 6A. For the output of the second pressure sensor SP2,similarly, correction data for the second pressure sensor SP2 is readout from the PROM 8, the span and the zero point are nonlinearlyadjusted, a process for correcting the temperature by the output of thetemperature sensor ST is executed, the processed signal is outputted tothe PWM 5B and an output 2 is obtained from the LPF 6B.

[0285] Consequently, according to the embodiment of FIG. 13 as well, thesame effects as those in the foregoing embodiment can be obtained. Evenwhen the number of sensors is large, the characteristics of the digitalsystem can be sufficiently utilized by hardly enlarging the hardwarescale and the characteristics of the sensor can be adjusted with highaccuracy.

[0286] According to the embodiment of the invention as mentioned above,the first stage amplification function and the A/D converting functionare obtained by performing the ΔΣ modulation to the output of the sensorand the D/A converting function is obtained by the PWM and the filteroperation. Consequently, the functional overhang is suppressed and thecircuit-scale can be reduced. Thus, the digital signal processor havinga very accurate characteristic which can be easily formed on a chip canbe provided at low cost.

What is claimed is:
 1. A sensor adjusting circuit for adjusting ananalog input signal inputted from a sensor in accordance with a physicalquantity to be sensed and outputting the analog input signal as anotheranalog output signal, comprising: a first analog-to-digital converterhaving an analog integrator for integrating said analog input signal, acomparator for comparing an output of said analog integrator with apredetermined value, and a D/A converter for outputting an output ofsaid comparator as said input signal; and a second digital-to-analogconverter for D/A converting the output of said comparator andoutputting resultant data as said analog output signal.
 2. A circuitaccording to claim 1, further comprising an operational unit fordigitally processing the output of said comparator and outputtingresultant data to said second digital-to-analog converter.
 3. A sensoradjusting circuit comprising an analog-to-digital converter, anoperational unit for processing an output of said analog-to-digitalconverter by a prestored program, and a writable memory for holding datafor adjustment, wherein said analog-to-digital converter is constructedby an oversampling analog-to-digital converter including an analogintegrator, a comparator, and a digital-to-analog converter, and saidoversampling analog-to-digital converter is constructed to generate anoutput having the number of bits which is equal to or lower than anaccuracy required by a sensor as an object in a cycle which is equal toor faster than {fraction (1/10)} of a response cycle required by saidsensor.
 4. A sensor adjusting circuit comprising an analog-to-digitalconverter, an operational unit for processing an output of saidanalog-to-digital converter by a prestored program, and a writablememory for holding data for adjustment, wherein said analog-to-digitalconverter is constructed by an oversampling analog-to-digital converterincluding an analog integrator, a comparator, and a digital-to-analogconverter, and said oversampling analog-to-digital converter hasconversion accuracy of 4 or 8 bits.
 5. A sensor adjusting circuitcomprising an analog-to-digital converter, an operational unit forprocessing an output of said analog-to-digital converter by a prestoredprogram, and a writable memory for holding data for adjustment, whereinsaid analog-to-digital converter is constructed by an oversamplinganalog-to-digital converter including an analog integrator, acomparator, and a digital-to-analog converter, and said oversamplinganalog-to-digital converter constructs a part of a sensor circuit of asensor as an object.
 6. A sensor adjusting circuit comprising ananalog-to-digital converter, an operational unit for processing anoutput of said analog-to-digital converter by a prestored program, and awritable memory for holding data for adjustment, wherein saidanalog-to-digital converter is constructed by an oversamplinganalog-to-digital converter including an analog integrator, acomparator, and a digital-to-analog converter, said oversamplinganalog-to-digital converter generates an output having the number ofbits which is equal to or less than an accuracy required by a sensor asan object in a cycle which is equal to or faster than {fraction (1/10)}of a response cycle required by said sensor, and an average value ofoutputs of said operational unit satisfies the requirement of saidsensor.
 7. A circuit according to any one of claims 3 to 6, wherein saidoperational unit is operated by a cyclic program which cycles fromaddress 0 to address of the maximum counting value of a program counterso that a reset upon turn-on of a power source is unnecessary.
 8. Acircuit according to any one of claims 3 to 6, wherein said writablememory which holds data for adjustment has an error correction logic andan error detection logic.
 9. A digital sensor adjusting circuit foradjusting an output of a sensor for sensing a physical quantity byprocessing the output of the sensor with prestored data forcharacteristic adjustment, comprising: an analog integrator forintegrating and outputting an output of said sensor; a comparator forconverting outputs of said analog integrator into digital signals oflevel 1 and 0; a 1-bit D/A converter for converting an output of saidcomparator into an analog signal and outputting the analog signal; and asubtracter for subtracting an output of said 1-bit D/A converter from aninput of said analog integrator, wherein the output of said comparatoris processed with said prestored data for characteristic adjustment,thereby adjusting an output of said sensor.
 10. A digital sensoradjusting circuit for adjusting an output of a sensor for sensing aphysical quantity by a numerical process by a prestored program,comprising: a ROM for storing a program; a RAM for temporarily storingdata; an accumulator for temporarily storing data for data transfer; adata bus for connecting at least said accumulator and said RAM; and aprogram counter for controlling execution of a program, wherein saidprogram counter is always counted up except for a subtrahend due to anoverflow and said ROM for storing programs is connected to a data busdifferent from said data bus.
 11. A digital sensor adjusting circuit foradjusting an output of a sensor for sensing a physical quantity by anumerical operation of a prestored program, comprising: a ROM forstoring a program; a RAM for temporarily storing data; an accumulatorfor temporarily storing data for data transfer; a data bus forconnecting at least said accumulator and said RAM; and at least twoprogram counters for controlling execution of a program, wherein meansfor controlling the program counter which is valid at present isprovided.
 12. A digital sensor adjusting circuit for adjusting an outputof a sensor for sensing a physical quantity by a numerical process of aprestored program, comprising: a ROM for storing a program; a RAM fortemporarily storing data; an accumulator for temporarily storing datafor data transfer; a data bus for connecting at least said accumulatorand said RAM; and an operational unit for executing a numericaloperation, wherein said operating unit is connected to said data bus.13. A digital sensor adjusting circuit for adjusting an output of asensor for sensing a physical quantity by a numerical process of aprestored program, comprising: a ROM for storing a program; a RAM fortemporarily storing data; an accumulator for temporarily storing datafor data transfer; a data bus for connecting at least said accumulatorand said RAM; and an operational unit for executing a numericaloperation, wherein writing to said accumulator is inhibited according toan internal state of said operational unit.